In-Depth FPGA Interfacing of HD44780 Based LCD

This project illustrates the interfacing of a HD44780 based LCD to the Xilinx Spartan-2 XCS200 FPGA using delayed Finite State Machine (FSM). While using a microcontroller to display text on the LCD is a fairly simple task, interfacing the LCD with a programmable logic device is a different story. The FSM controls the timing and generation of the signals required for data communication, making the process a lot easier.

The HD44780 LCD uses minimum 2.2V voltage for logic ‘1’ and maximum 0.6V voltage for logic ‘0’ for a given Vcc of 4.5 to 5.5V. These voltages are easily managed by the FPGA, using LVTTL mode. The project makes use of the write operation only in communicating with the LCD, so the RW pin is not used. The execution time delay, used to determine that the current write operation is completed, is 40ns. A 4-bit counter is used to control the instructions (the counter is controlled with the CE signal).

When electrical power is applied to the circuit the FSM enters its first state, the Pwr_Up state (check the diagram). The next state is the Pwr_Up_Delay state which lasts 45ms. The device has a multiplexer that puts the CE signal of the counter on high during these two first states. The next state is the Off_Pwr_Up_Delay, after which the FSM enters the Write_Data state (Enable pulse generation state machine). Next is the Data_Setup_Delay state, in which a delay is generated to make sure the setup time before the rising edge of the Enable pulse is adequate.

The Enable must has to be at least 240ns to be valid, and this is handled in the E_Pulse_Hi, E_Hi_Time and E_Pulse_Lo states. The E pin of the LCD is set on high during E_Pulse_Hi and E_Hi_Time states, and low on E_Pulse_Lo state. The next state is the Proc_Comp_Delay state, in which the delay for the current instruction is activated. The next state is Load_Next_Data and the FSM can either move back to Write_Data state and continue to send instructions to the LCD or go to the End_State.

The FSM and hardware layout is using the Xilinx ISE 8.1i VHDL Compiler. Check the article for a pdf file with additional instructions, diagrams and schematics and look into the datasheet of the HD44780 Based LCD for detailed specifications.

In-Depth FPGA Interfacing of HD44780 Based LCD: [Link][Link2]