Graphic LCD Pannel Interfaced With FPGA

FPGAs make great video controllers and can easily control graphic LCD panels. Graphic LCD panels are more advanced than text lcd panels and can display interesting stuff. The graphic LCD panels have a digital interface and can be interfaced in two ways:

  1. With a Video-like interface
  2. With a CPU-peripheral-like interface

Graphic LCD Pannel Interfaced With FPGA: [Link]

68HC000 Home Made Computer

You grab a Motorola 68HC000 32 bit mcu some knowledge you mix them together and you should get a 32-bit power single board computer. The chip is quite old but there are many chip makers still produce it.

he 68000 Single Board Computer features:

  • CPU: 68HC000 68-pin PLCC @8MHz,
  • Memory: SRAM 256kB (6281282), FLASH 256kB (29C010x2),
  • GPIO: 8-bit output port, 8-bit input port,
  • UART: 6850 9600 8n1,
  • RTC: DS12887,
  • Glue logic: DTACK, memory/io decoder, Xilink XC9572 CPLD,
  • Monitor program:  zBug V1.0 for 68000-Based Single Board Computer.

68HC000 Home Made Computer: [Link]

April 19th, 2008

Wlan for AVR

 Wlan for AVR board

The entire system consists of three main function blocks: The AVR as the central CPU running the high level network routines including the TCP/IP stack. The second main block is the compact flash WLAN card running all the low level network functions including encryption. The third block is a XC9572XL CPLD, a programmable logic device that forms the spi2cf interface between the AVRs SPI and the CF card. It is mainly doing the translation between the SPI interface used to connect to the AVR and the parallel interface used on the compact flash slot.

Wlan for AVR: [Link]

April 3rd, 2008

Snake robot named Snaky

 Snake robot named Snaky - module closeup

Snaky is built around a powerful ATMEGA88 AVR microcontroller from Atmel, twelve miniature servo-motors and a few other components. On the software side the most CPU intensive section is the PWM generation, as 12 PWM signals are generated with a resolution of 20μs and a quite high pulse refresh rate. To achieve this target an innovative firmware architecture is implemented, managing two PWM channels at a time.

Snake robot named Snaky:[Download Project][View Project PDF]

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